module Reg_MEM_WB (
    input wire clk,
    input wire rst,

    input wire [31:0] MEM_ALU_C,
    input wire [31:0] MEM_DRAMrd2RF,
    input wire [31:0] MEM_sext_ext,
    input wire [4:0] MEM_RF_waddr,
    input wire [31:0] MEM_pc,
    input wire [31:0] MEM_pc4,
    input wire MEM_rf_we,
    input wire [1:0] MEM_rf_wsel,

    output reg [31:0] WB_ALU_C,
    output reg [31:0] WB_DRAMrd2RF,
    output reg [31:0] WB_sext_ext,
    output reg [4:0] WB_RF_waddr,
    output reg [31:0] WB_pc,
    output reg [31:0] WB_pc4,
    output reg WB_rf_we,
    output reg [1:0] WB_rf_wsel


);

always @(posedge clk or posedge rst) begin
    if(rst) WB_ALU_C <= 0;
    else WB_ALU_C <= MEM_ALU_C; 
end

always @(posedge clk or posedge rst) begin
    if(rst) WB_DRAMrd2RF <= 0;
    else WB_DRAMrd2RF <= MEM_DRAMrd2RF; 
end

always @(posedge clk or posedge rst) begin
    if(rst) WB_sext_ext<= 0;
    else WB_sext_ext<= MEM_sext_ext; 
end

always @(posedge clk or posedge rst) begin
    if(rst) WB_RF_waddr <= 0;
    else WB_RF_waddr <= MEM_RF_waddr; 
end

always @(posedge clk or posedge rst) begin
    if(rst) WB_pc<= 0;
    else WB_pc<= MEM_pc; 
end

always @(posedge clk or posedge rst) begin
    if(rst) WB_pc4<= 0;
    else WB_pc4<= MEM_pc4; 
end

always @(posedge clk or posedge rst) begin
    if(rst) WB_rf_we<= 0;
    else WB_rf_we<= MEM_rf_we; 
end

always @(posedge clk or posedge rst) begin
    if(rst) WB_rf_wsel <= 0;
    else WB_rf_wsel<= MEM_rf_wsel; 
end
    
endmodule